Nervous System

Design space Explorer

Space Exploration / April 29, 2020

Design Space Explorer II (DSE) is a simple and easy-to-use design optimization utility that leverages a new exploration engine. DSE II is included with the Quartus® II software v14.1 and later. DSE II explores and reports the results of your optimization focus for a design. You can target design performance, area utilization, or power dissipation improvements.

DSE II uses predefined Quartus II compiler settings that make it easy to determine the optimal settings for a particular design.

The following lists the objectives of this design example:

  • Run a default Quartus II compilation flow on a design example
  • Run a DSE II exploration flow on a design example
  • Learn how the DSE II GUI and exploration options can help you find the optimal settings for your design

This example was developed using the Quartus II software v14.1 running on a PC. This archived design example has an OpenCore Ethernet media access control (MAC) instance targeted to a Stratix® V device. The core is constrained within a LogicLockTM region in the selected device.

Default Compilation

To run the default compilation, perform the following steps:

  1. Download the MAC_top.qar project archive file and save it to your computer.
  2. Start Quartus II GUI and un-archive the design. To restore the archived project, from the Project menu, click Restore Archived Project, and point to the archive file location.
  3. Use the default directory name prompted in the dialog box, and click OK.
  4. To compile the project with default settings, from the Processing menu, click on the Start Compilation icon on the Quartus II GUI to compile the design. The compilation takes a few minutes to complete.
  5. After the compilation completes, from the Processing menu, click Compilation Report to open the Compilation Report panel.
  6. Click on the sign next to the TimeQuest Timing Analyzer report section under the compilation report to view the timing failures. You will see that the design has setup and hold violations on the Clk_reg, Rx_clk andClk_125M domains. Figure 1 shows a screenshot of the report from the Multicorner Timing Analysis Summary.